Conventionally, various methods for manufacturing a plurality of semiconductor chips by dividing such a semiconductor wafer have been known. For example, a method is known of collectively forming semiconductor devices in a plurality of device-formation-regions provided on a wafer of single-crystal silicon or the like, mechanically cutting (i.e., by dicing) the wafer along dividing regions located between adjacent device-formation-regions and manufacturing semiconductor chips by individualizing the device-formation regions.
Moreover, in such a wafer, an evaluation device (test device) that is called a Test Element Group (TEG) is formed in the dividing regions. In various processes of the semiconductor chip manufacturing process, the actual device characteristics are monitored by investigating various characteristics by means of the thus-formed TEG.
Moreover, it is often the case where such a TEG is formed of a material that contains various kinds of metals and inorganic substances besides silicon and silicon oxide that are generally the principal materials of the wafer. Moreover, the formed TEG becomes unnecessary after the various characteristics are investigated, and the TEG is removed by cutting (or dicing) in the stage of wafer dicing along the dividing regions.
Although shrinkage (narrowing) of the dividing region has been promoted to increase the number of semiconductor chips obtainable per a wafer or to expand the device-formation-regions in recent years, there is a limitation in narrowing the width of the TEG formation region from the viewpoint of reliably carrying out various electrical measurements. Therefore, the dividing regions are narrowed by reducing a gap between the edge portion of the TEG formation region and the edge portion of the dividing regions.
On the other hand, generating minute fragments (chipping) or generating minute cracks (microcracks) is easily caused by impacts during cutting by a blade during wafer dicing, and therefore, it is necessary to carry out the cutting by the blade in a position located apart from the device-formation-region by some degree. Therefore, if the narrowing of the dividing regions as described above is promoted, the TEG cannot completely be removed by the cutting. If the TEG remains partially unremoved, short circuiting or the like occurs due to the contact of the TEG with the wiring pattern when the semiconductor chip is mounted, and thus it is a concern that the problem of circuit failure might occur.
In order to suppress the occurrence of these problems, various methods have been considered as a method for removing the TEG by cutting, as disclosed in, for example, Japanese unexamined patent publication No. 2002-231659 and No. 2001-60568.